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sn74lv1t00 scls737b ? september 2013 ? revised february 2014 sn74lv1t00 single power supply 2-input positive nand gate cmos logic level shifter 1 features 2 applications 1 ? single-supply voltage translator at ? industrial controllers 5.0/3.3/2.5/1.8v v cc ? telecom ? operating range of 1.8v to 5.5v ? portable applications ? up translation ? servers ? 1.2v (1) to 1.8v at 1.8v v cc ? pc and notebooks ? 1.5v (1) to 2.5v at 2.5v v cc ? automotive ? 1.8v (1) to 3.3v at 3.3v v cc 3 description ? 3.3v to 5.0v at 5.0v v cc sn74lv1t00 is a low voltage cmos gate logic that ? down translation operates at a wider voltage range for industrial, ? 3.3v to 1.8v at 1.8v v cc portable, telecom, and automotive applications. the ? 3.3v to 2.5v at 2.5v v cc output level is referenced to the supply voltage and is able to support 1.8v/2.5v/3.3v/5v cmos levels. ? 5.0v to 3.3v at 3.3v v cc the input is designed with a lower threshold circuit to ? logic output is referenced to v cc match 1.8v input logic at v cc = 3.3v and can be used ? output drive in 1.8v to 3.3v level up translation. in addition, the ? 8ma output drive at 5v 5v tolerant input pins enable down translation (e.g. ? 7ma output drive at 3.3v 3.3v to 2.5v output at v cc = 2.5v). the wide v cc range of 1.8v to 5.5v allows generation of desired ? 3ma output drive at 1.8v output levels to connect to controllers or processors. ? characterized up to 50mhz at 3.3v v cc the sn74lv1t00 is designed with current-drive ? 5v tolerance on input pins capability of 8 ma to reduce line reflections, ? ? 40 c to 125 c operating temperature range overshoot, and undershoot caused by high-drive ? pb-free packages available: sc-70 (dck) outputs. ? 2 2.1 0.65 mm device information ? latch-up performance exceeds 250ma order number package body size per jesd 17 sn74lv1t00dbvr sot-23 (5) 2,90mm x 1,60mm ? esd performance tested per jesd 22 sn74lv1t00dckr sc70 (5) 2,00mm x 1,25mm ? 2000-v human-body model (a114-b, class ii) dck or dbv package ? 200-v machine model (a115-a) (top view) ? 1000-v charged-device model (c101) ? supports standard logic pinouts ? cmos output b compatible with aup1g and lvc1g families (1) refer to the v ih /v il and output drive for lower v cc condition. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder a b gnd v cc y 1 2 3 5 4 support &community tools & software technical documents sample &buy
sn74lv1t00 scls737b ? september 2013 ? revised february 2014 www.ti.com table of contents 4.6 operating characteristics ......................... 7 1 features ................................................................. 1 5 parameter measurement information ................. 8 2 applications .......................................................... 1 5.1 more product selection ............................................ 8 3 description ............................................................ 1 6 device and documentation support ................... 9 4 revision history ................................................... 2 6.1 trademarks .............................................................. 9 4.1 typical design examples ......................................... 5 6.2 electrostatic discharge caution ............................... 9 4.2 absolute maximum ratings ..................................... 5 6.3 glossary ................................................................... 9 4.3 recommended operating conditions ...................... 6 7 mechanical, packaging, and orderable 4.4 electrical characteristics .......................................... 6 information ............................................................ 9 4.5 switching characteristics ........................................ 7 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (september 2013) to revision a page ? updated v cc values for v ih parameter in the electrical characteristics table. .................................................... 6 changes from revision a (september 2013) to revision b page ? updated document formatting. .............................................................................................................................................. 1 2 submit documentation feedback copyright ? 2013 ? 2014, texas instruments incorporated product folder links: sn74lv1t00
sn74lv1t00 www.ti.com scls737b ? september 2013 ? revised february 2014 function table input output (lower level input) (v cc cmos) a b y h h l l x h x l h supply v cc = 3.3v a b y v ih (min) =1.35 v v oh (min) = 2.9 v v il (max) =0.8 v v ol (max)= 0.2 v figure 1. logic diagram (nand gate) figure 2. excellent signal integrity (1.8v to 3.3v at 3.3v v cc ) copyright ? 2013 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: sn74lv1t00 a b 1 2 4 y
sn74lv1t00 scls737b ? september 2013 ? revised february 2014 www.ti.com figure 3. excellent signal integrity (3.3v to 3.3v at 3.3v v cc ) figure 4. excellent signal integrity (3.3v to 1.8v at 1.8v v cc ) 4 submit documentation feedback copyright ? 2013 ? 2014, texas instruments incorporated product folder links: sn74lv1t00
sn74lv1t00 www.ti.com scls737b ? september 2013 ? revised february 2014 4.1 typical design examples figure 5. switching thresholds for 1.8-v to 3.3-v translation 4.2 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ? 0.5 7.0 v v i input voltage range (2) ? 0.5 7.0 v voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 4.6 v v o voltage range applied to any output in the high or low state (2) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 20 ma i ok output clamp current v o < 0 or v o > v cc 20 ma i o continuous output current 25 ma continuous current through vcc or gnd 50 ma dbv package 206 package thermal ja impedance (3) dck package 252 c/w t stg storage temperature range ? 65 150 c (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the package thermal impedance is calculated in accordance with jesd 51-7. copyright ? 2013 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: sn74lv1t00 vih min = 1.36v vil min = 0.8v voh min = 2.4v vol max = 0.4v lv1txx logic 3.3v system 5.0v, 3.3v 2.5v, 1.8v system vcc = 3.3v lv1txx logic vcc = 5.0v 5.0v 3.3v system 5.0v system vih = 2.0v vil = 0.8v lv1txx logic vcc = 1.8v 5.0v, 3.3v 2.5v, 1.8v 1.5v, 1.2v system 1.8v system vih = 0.99v vil = 0.55v
sn74lv1t00 scls737b ? september 2013 ? revised february 2014 www.ti.com 4.3 recommended operating conditions (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage 1.6 5.5 v v i input voltage 0 5.5 v v o output voltage 0 v cc v v cc = 1.8 v ? 3 v cc = 2.5 v ? 5 i oh high-level output current ma v cc = 3.3 v ? 7 v cc = 5.0 v ? 8 v cc = 1.8 v 3 v cc = 2.5 v 5 i ol low-level output current ma v cc = 3.3 v 7 v cc = 5.0 v 8 v cc = 1.8 v 20 input transition rise or fall t/ v v cc = 3.3 v or 2.5v 20 ns/v rate v cc = 5.0 v 20 t a operating free-air temperature ? 40 125 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004 . 4.4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) t a = 25 c t a = ? 40 c to 125 c parameter test conditions v cc unit min typ max min max v cc = 1.65 v to 1.8 v 0.94 1.0 v cc = 2.0 v 1.02 1.03 v cc = 2.25 v to 2.5 v 1.135 1.18 v cc = 2.75 v 1.21 1.23 high-level input v ih v voltage v cc = 3 v to 3.3 v 1.35 1.37 v cc = 3.6 v 1.47 1.48 v cc = 4.5 v to 5.0 v 2.02 2.03 v cc = 5.5 v 2.1 2.11 v cc = 1.65 v to 2.0 v 0.58 0.55 v cc = 2.25 v to 2.75 v 0.75 0.71 low-level input v il v voltage v cc = 3 v to 3.6 v 0.8 0.65 v cc = 4.5 v to 5.5 v 0.8 0.8 i oh = ? 20 a 1.65 v to 5.5 v v cc ? 0.1 v cc ? 0.1 v 1.65 v 1.28 1.21 i oh = ? 2.0 ma v 1.8v 1.5 1.45 i oh = ? 2.3 ma 2 2 2.3v v i oh = ? 3 ma 2 1.93 i oh = ? 3 ma 2.5v 2.25 2.15 v v oh i oh = ? 3.0 ma 2.78 2.7 3.0 v i oh = ? 5.5 ma 2.6 2.49 v i oh = ? 5.5 ma 3.3 v 2.9 2.8 i oh = ? 4 ma 4.2 4.1 4.5 v i oh = ? 8 ma 4.1 3.95 v i oh = ? 8 ma 5.0 v 4.6 4.5 6 submit documentation feedback copyright ? 2013 ? 2014, texas instruments incorporated product folder links: sn74lv1t00
sn74lv1t00 www.ti.com scls737b ? september 2013 ? revised february 2014 electrical characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) t a = 25 c t a = ? 40 c to 125 c parameter test conditions v cc unit min typ max min max i ol = 20 a 1.65 v to 5.5 v 0.1 0.1 i ol = 1.9 ma 1.65 v 0.2 0.25 i oh = 2.3 ma 0.1 0.15 2.3v i oh = 3 ma 0.15 0.2 v ol i ol = 3 ma 0.1 0.15 3.0 v i ol = 5.5 ma 0.2 0.252 v i ol = 4 ma 0.15 0.2 4.5 v i ol = 8 ma 0.3 0.35 i i a input v i = 0 v or v cc 0v, 1.8v, 2.5v, 3.3v, 5.5 v 0.12 1 a 5.0 v 1 10 3.3 v 1 10 v i = 0 v or v cc , i cc a i o = 0; open on loading 2.5 v 1 10 1.8v 1 10 one input at 0.3v or 3.4v, other inputs at 0 or v cc , 5.5 v 1.35 1.5 ma i o = 0 i cc one input at 0.3v or 1.1v other inputs at 0 or v cc , 1.8v 10 10 a i o = 0 c i v i = vcc or gnd 3.3 v 2 10 2 10 pf c o v o = v cc or gnd 3.3 v 2.5 2.5 pf 4.5 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 7 ) t a = 25 c t a = ? 65 c to 125 c from to frequency parameter v cc c l unit (input) (output) (typ) min typ max min typ max 15pf 4 5 4 5 5.0v ns 30pf 5.5 7.0 5.5 7.0 dc to 50 mhz 15pf 4.8 5 5 5.5 3.3v ns 30pf 5 5.5 5.5 6.5 t pd any in y 15pf 6 6.5 7 7.5 dc to 25 mhz 2.5v ns 30pf 6.5 7.5 7.5 8.5 15pf 10.5 11 11 12 dc to 15 mhz 1.8v ns 30pf 12 13 12 14 4.6 operating characteristics t a = 25 c parameter test conditions v cc typ unit 1.8 v 0.15 v 10 2.5 v 0.2 v 10 c pd power dissipation capacitance f = 1 mhz and 10 mhz pf 3.3 v 0.3 v 10 5.5 v 0.5 v 10 copyright ? 2013 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: sn74lv1t00
sn74lv1t00 scls737b ? september 2013 ? revised february 2014 www.ti.com 5 parameter measurement information figure 6. load circuit and voltage waveforms 5.1 more product selection device package description sn74lv1t00 dck, dbv 2-input positive-nand gate sn74lv1t02 dck, dbv 2-input positive-nor gate sn74lv1t04 dck, dbv inverter gate sn74lv1t08 dck, dbv 2-input positive-and gate sn74lv1t17 dck, dbv single buffer gate with 3-state output sn74lv1t14 dck, dbv single schmitt-trigger inverter gate sn74lv1t32 dck, dbv 2-input positive-or gate sn74lv1t50 dck, dbv single buffer gate with 3-state output sn74lv1t86 dck, dbv single 2-input exclusive-or gate sn74lv1t125 dck, dbv single buffer gate with 3-state output sn74lv1t126 dck, dbv single buffer gate with 3-state output sn74lv4t125 rgy, pw quadruple bus buffer gate with 3-state outputs 8 submit documentation feedback copyright ? 2013 ? 2014, texas instruments incorporated product folder links: sn74lv1t00 v mi from output under t est c l (see note a) load circuit 1 m volt age w aveforms propaga tion dela y times inverting and noninverting outputs t plh t phl t phl t plh v oh v oh v ol v ol v i 0 v input outputoutput notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , slew rate 1 v/ns. c. the outputs are measured one at a time, with one transition per measurement. d. t plh and t phl are the same as t pd . v mo v mo v mo v mo v mi v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v c l v mi v mo 5, 10, 15, 30 pf v i /2 v cc /2 5, 10, 15, 30 pf v i /2 v cc /2
sn74lv1t00 www.ti.com scls737b ? september 2013 ? revised february 2014 6 device and documentation support 6.1 trademarks all trademarks are the property of their respective owners. 6.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 6.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 7 mechanical, packaging, and orderable information the following packaging information and addendum reflect the most current data available for the designated devices. this data is subject to change without notice and revision of this document. copyright ? 2013 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: sn74lv1t00
package option addendum www.ti.com 21-feb-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74lv1t00dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (nea3 ~ neas) sn74lv1t00dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (wa3 ~ was) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 21-feb-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lv1t00dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74lv1t00dbvr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lv1t00dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lv1t00dckr sc70 dck 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 q3 package materials information www.ti.com 3-aug-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74lv1t00dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 sn74lv1t00dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lv1t00dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lv1t00dckr sc70 dck 5 3000 202.0 201.0 28.0 package materials information www.ti.com 3-aug-2017 pack materials-page 2

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
package option addendum www.ti.com 5-jun-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74lv1t00dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (nea3, neas) SN74LV1T00DBVRG4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 nea3 sn74lv1t00dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (wa3, was) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 5-jun-2018 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lv1t00dbvr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lv1t00dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 SN74LV1T00DBVRG4 sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lv1t00dckr sc70 dck 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 q3 sn74lv1t00dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 package materials information www.ti.com 29-may-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74lv1t00dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lv1t00dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 SN74LV1T00DBVRG4 sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lv1t00dckr sc70 dck 5 3000 202.0 201.0 28.0 sn74lv1t00dckr sc70 dck 5 3000 180.0 180.0 18.0 package materials information www.ti.com 29-may-2018 pack materials-page 2

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

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